166 to 180 of 251
Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research activities in digital signal processing for SerDes and optical channels. Work with designers to ensure circuit architec
Posted 16 days ago
Familiarization with Marvell Coherent DSP products Capture candidate solution architectures Test and troubleshoot solutions in the lab using python scripting Document the results Requirements Candidate MUST be currently pursuing a BS/MS (preferred) degree in CS/EE or related technical field(s) 0 1 years of previous experience The Perks With competitive compensation and gr
Posted 16 days ago
Learn how to work independently and methodologically using industry standard tools Participate in the development of characterization and validation tests along with multidiscipline engineers such as HW, FW, validation engineers Perform validation of next generation ODSP products in a supportive and dynamic environment Develop automation to support data collection Support
Posted 16 days ago
Create test plans from the product requirement definitions and datasheet Devise test setups, support design of probe hardware, test sockets and PCB's Develop test software in Python to support product sampling, reliability qualification and characterization Hands on measurement of electrical and optical IC's. Perform test reproducibility and repeatability Analyze test dat
Posted 16 days ago
Understanding the requirements of the product Basic Understanding for backend flow (Fab, Sort, Assembly, Package test on ATE and SLT) Basic understanding of production and test flow Involve in basic checkout of test program and debug activities on ATE Data parsing and understanding of correlation between different flows Develop basic debug skill on ATE and SLT Develop scr
Posted 16 days ago
Implement modern DFT solutions for leading edge ICs on latest technology nodes. Understand and then implement the Marvell DFT architecture Work with RTL, custom digital/analog, verification, physical implementation, and timingteams duringthis DFT implementation. Set up, run, and debug block level, SOC level as well as full chip ATPG runs Drive successful bring up of test
Posted 16 days ago
In this role, the Director of Supply Chain Master Planning will motivate, lead, and guide master planners to continue developing processes and tools, working with IT, supply chain business systems, and other planning organizations for planning efficiency. This role requires strong collaboration with internal and external partners to ensure the translation of demand into s
Posted 16 days ago
Support failure analysis for both customer returns and internal product development support. Work with internal cross functional teams for root cause investigations and fault isolation. Hands on work to support incoming rework and lab analysis. Work with external FA labs to perform physical failure analysis. Support and work with internal teams to drive corrective action
Posted 16 days ago
Responsibilities Work closely with mentors and other team members to define the project scope Successfully implement an improved chip sizing process Document and present to engineering and executive teams the results of the project Meet people and learn and the industry Requirements Minimum Qualifications Candidate MUST be currently pursuing a BS/MS (preferred) degree in
Posted 16 days ago
Review critical nets, such as clock and high speed interfaces, and determine the areas of concerns for in depth analysis to ensure signal quality. Construct simulation models from extracted circuit and paths of chip, package, and possibly PCB. Perform simulation, analyze the results, and review with the design team. Change key parameters in simulation to study the effects
Posted 16 days ago
Assist ASIC BU and customers on IP selections accordingly to product requirements. Assist customers and design teams on design integration of the IPs, logically and physically. Conduct IP usage reviews and design sign of with customers and design teams. Provide assistance on hardware test and hardware bring up debug. Lead lesson learn with Design Center teams and IP devel
Posted 16 days ago
Responsibilities Develop and support Marvell's block level and partition level construction and signoff flows, incorporating industry standard EDA tools Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks Develop and implement timing and logic ECOs Interact with the RTL design team to drive design modifications to resolve congestion and tim
Posted 16 days ago
Overview into the maturity of a High Speed 100G PAM4 products from conception phase into Mass production Phase. Application engineering activities involve working with lead customers, to understand / replicate issues; interface with Design/ Analog / validation leads to break down the issue; propose a final solution and work with customers to resolve the issue. Hands on la
Posted 16 days ago
Implement modern DFT solutions for leading edge ICs on latest technology nodes. Understand and then implement the Marvell DFT architecture Work with RTL, custom digital/analog, verification, physical implementation, and timingteams duringthis DFT implementation. Set up, run, and debug block level, SOC level as well as full chip ATPG runs Drive successful bring up of test
Posted 16 days ago
Responsibilities Work on real world business problems and solutions Assist in financial system updates, modeling and business case scenarios Collaborate with other finance departments and accounting in monthly/quarterly finance cycles Create new dashboards to drive efficiency across the organization Requirements Minimum Qualifications Currently enrolled in MBA program wit
Posted 16 days ago
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