At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
The OpportunityCentral Engineering ASIC Design Services in Marvell develops chips for external customers in market segments such as next generation 5G carriers, cloud data centers, enterprise networking, and automotive. We are looking for an experienced static timing design engineer who will help with the design, analysis, and implementation of timing fixes on system-on-chip (SOC) designs to ensure successful delivery to end client.
Timing close SOC design based off customer requirements and specification.
Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages).
Analyze, debug, and implement fixes for reported timing violations (setup, hold, slew, and capacitance) using defined CAD tools/flow.
Collaborate with global CAD teams on design flow fixes and feature improvements.
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Experienced in STA practices and concepts, such as timing sign-off, timing takedown, noise-induced events, Miller-capacitance, etc.
Experience with STA flow and CAD tools, such as Synopsys Primetime, Cadence Tempus, and experience in using them in an beginning-to-end project setting in a recent semiconductor technology nodes - 7nm/10nm and 14nm/16nm.
Ability to write and debug timing constraints for complex IP and complex timing situations.
Excellent English communication skill in verbal and written.
Able to work effectively with global team and be self-motivated to solve problems and manage deliverables.
Thorough understanding of Linux/Unix/BSD Internals, with experience working on Multi-threaded systems.
Experience using distritbuted processing for timing
Understanding of and/or developement of sign-off criteria and margins
Experience coorelating timing results to spice and other timing tools
Excellent programming Skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills.The Perks
With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.Your Future
Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or 408-222-3604.