At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Job Responsibilities:

Responsibilities:

*Develop and support Marvell's block-level and partition-level construction and signoff flows, incorporating industry standard EDA tools

*Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks

*Develop and implement timing and logic ECOs

*Interact with the RTL design team to drive design modifications to resolve congestion and timing issues

*Work with the global timing team in debugging/resolving any block-level timing issues seen at full chip

*Interact with tool vendors to drive tool improvements and perform tool evaluations of new tools/functions

Requirements:

As a physical designengineer in Marvell's Processor Business Group, you will play a leading role in developing next-generation automated design flows and using these flows to drive design closure.

Minimum Qualifications

*Experience with Cadence Innovus (preferred) or other industry tools

*Experience creating and/or supporting EDA/CAD automation

*Strong proficiency in Tcl, Perl and/or Python with experience in at least one of these in the context of flow development.

*Understanding of programming principles such as object-oriented programming, multi-threading and data structures.

*Deep understanding of standard RTL to GDS flows and methodology

*Good analysis and problem-solving skills. Out-of-the-box thinking

*Team player with good verbal and written communication skills.

Education

*Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.

*Master's degree and/or PhD in Computer Engineering, Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

Preferred Qualification:

*Experience with:

oTiming analysis and closure methods

oTops-down hierarchical floorplanning

oRoute planning and routability issue resolution

oPower grid design and validation

oVarious clock synthesis schemes

oSI, EM/IR, complex DRC rules

oPower intent and implementation of multiple power domains

oHigh speed and low power implementation techniques/trade-offs

oGate-to-gate equivalence checking

oParasitic extraction

#LI-KL1

With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or 408-222-3604.